Seich
/
TFT_eSPI
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Eliminate need for TFT_DATA_PIN_OFFSET_EN in setup file

This commit is contained in:
Bodmer 2023-01-06 15:59:47 +00:00 committed by GitHub
parent 60e8e97d2b
commit 869cfc28c9
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
Processors/TFT_eSPI_ESP32_S3.h
View File

@ -351,14 +351,14 @@ SPI3_HOST = 2
//////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////
#if defined (TFT_PARALLEL_8_BIT) #if defined (TFT_PARALLEL_8_BIT)
#if defined(TFT_DATA_PIN_OFFSET_EN) /* Micky modifies this to select the GPIO control register - 20220701 */ #if (TFT_D0 >= 32) // If D0 is a high GPIO then assume all data bits use high GPIO
#define MASK_OFFSET 32 #define MASK_OFFSET 32
#define GPIO_CLR_REG GPIO.out1_w1tc.val #define GPIO_CLR_REG GPIO.out1_w1tc.val
#define GPIO_SET_REG GPIO.out1_w1ts.val #define GPIO_SET_REG GPIO.out1_w1ts.val
#else #else
#define MASK_OFFSET 0 #define MASK_OFFSET 0
#define GPIO_CLR_REG GPIO.out_w1tc #define GPIO_CLR_REG GPIO.out_w1tc
#define GPIO_SET_REG GPIO.out_w1ts #define GPIO_SET_REG GPIO.out_w1ts
#endif #endif
// Create a bit set lookup table for data bus - wastes 1kbyte of RAM but speeds things up dramatically // Create a bit set lookup table for data bus - wastes 1kbyte of RAM but speeds things up dramatically
@ -378,7 +378,7 @@ SPI3_HOST = 2
} \ } \
// Mask for the 8 data bits to set pin directions // Mask for the 8 data bits to set pin directions
#if defined(TFT_DATA_PIN_OFFSET_EN) #if (TFT_D0 >= 32) // If D0 is a high GPIO then assume all data bits use high GPIO
#define GPIO_DIR_MASK ((1 << (TFT_D0-MASK_OFFSET)) | (1 << (TFT_D1-MASK_OFFSET)) | (1 << (TFT_D2-MASK_OFFSET)) | (1 << (TFT_D3-MASK_OFFSET)) | (1 << (TFT_D4-MASK_OFFSET)) | (1 << (TFT_D5-MASK_OFFSET)) | (1 << (TFT_D6-MASK_OFFSET)) | (1 << (TFT_D7-MASK_OFFSET))) #define GPIO_DIR_MASK ((1 << (TFT_D0-MASK_OFFSET)) | (1 << (TFT_D1-MASK_OFFSET)) | (1 << (TFT_D2-MASK_OFFSET)) | (1 << (TFT_D3-MASK_OFFSET)) | (1 << (TFT_D4-MASK_OFFSET)) | (1 << (TFT_D5-MASK_OFFSET)) | (1 << (TFT_D6-MASK_OFFSET)) | (1 << (TFT_D7-MASK_OFFSET)))
#else #else
#define GPIO_DIR_MASK ((1 << TFT_D0) | (1 << TFT_D1) | (1 << TFT_D2) | (1 << TFT_D3) | (1 << TFT_D4) | (1 << TFT_D5) | (1 << TFT_D6) | (1 << TFT_D7)) #define GPIO_DIR_MASK ((1 << TFT_D0) | (1 << TFT_D1) | (1 << TFT_D2) | (1 << TFT_D3) | (1 << TFT_D4) | (1 << TFT_D5) | (1 << TFT_D6) | (1 << TFT_D7))