From 869cfc28c97317df70083cc5a15ad5851ab8d4ac Mon Sep 17 00:00:00 2001 From: Bodmer Date: Fri, 6 Jan 2023 15:59:47 +0000 Subject: [PATCH] Eliminate need for TFT_DATA_PIN_OFFSET_EN in setup file --- Processors/TFT_eSPI_ESP32_S3.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/Processors/TFT_eSPI_ESP32_S3.h b/Processors/TFT_eSPI_ESP32_S3.h index ddee7aa..213f4c7 100644 --- a/Processors/TFT_eSPI_ESP32_S3.h +++ b/Processors/TFT_eSPI_ESP32_S3.h @@ -351,14 +351,14 @@ SPI3_HOST = 2 //////////////////////////////////////////////////////////////////////////////////////// #if defined (TFT_PARALLEL_8_BIT) -#if defined(TFT_DATA_PIN_OFFSET_EN) /* Micky modifies this to select the GPIO control register - 20220701 */ -#define MASK_OFFSET 32 -#define GPIO_CLR_REG GPIO.out1_w1tc.val -#define GPIO_SET_REG GPIO.out1_w1ts.val +#if (TFT_D0 >= 32) // If D0 is a high GPIO then assume all data bits use high GPIO + #define MASK_OFFSET 32 + #define GPIO_CLR_REG GPIO.out1_w1tc.val + #define GPIO_SET_REG GPIO.out1_w1ts.val #else -#define MASK_OFFSET 0 -#define GPIO_CLR_REG GPIO.out_w1tc -#define GPIO_SET_REG GPIO.out_w1ts + #define MASK_OFFSET 0 + #define GPIO_CLR_REG GPIO.out_w1tc + #define GPIO_SET_REG GPIO.out_w1ts #endif // Create a bit set lookup table for data bus - wastes 1kbyte of RAM but speeds things up dramatically @@ -378,10 +378,10 @@ SPI3_HOST = 2 } \ // Mask for the 8 data bits to set pin directions - #if defined(TFT_DATA_PIN_OFFSET_EN) - #define GPIO_DIR_MASK ((1 << (TFT_D0-MASK_OFFSET)) | (1 << (TFT_D1-MASK_OFFSET)) | (1 << (TFT_D2-MASK_OFFSET)) | (1 << (TFT_D3-MASK_OFFSET)) | (1 << (TFT_D4-MASK_OFFSET)) | (1 << (TFT_D5-MASK_OFFSET)) | (1 << (TFT_D6-MASK_OFFSET)) | (1 << (TFT_D7-MASK_OFFSET))) + #if (TFT_D0 >= 32) // If D0 is a high GPIO then assume all data bits use high GPIO + #define GPIO_DIR_MASK ((1 << (TFT_D0-MASK_OFFSET)) | (1 << (TFT_D1-MASK_OFFSET)) | (1 << (TFT_D2-MASK_OFFSET)) | (1 << (TFT_D3-MASK_OFFSET)) | (1 << (TFT_D4-MASK_OFFSET)) | (1 << (TFT_D5-MASK_OFFSET)) | (1 << (TFT_D6-MASK_OFFSET)) | (1 << (TFT_D7-MASK_OFFSET))) #else - #define GPIO_DIR_MASK ((1 << TFT_D0) | (1 << TFT_D1) | (1 << TFT_D2) | (1 << TFT_D3) | (1 << TFT_D4) | (1 << TFT_D5) | (1 << TFT_D6) | (1 << TFT_D7)) + #define GPIO_DIR_MASK ((1 << TFT_D0) | (1 << TFT_D1) | (1 << TFT_D2) | (1 << TFT_D3) | (1 << TFT_D4) | (1 << TFT_D5) | (1 << TFT_D6) | (1 << TFT_D7)) #endif #if (TFT_WR >= 32)