Added T-DISPLAY-S3 i8080 support for more than 33 data pins (#2296)
* Modified the ESP32-S3 I8080 interface's support for data pins above 33 pins. * Added T-DISPLAY-S3 support
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Micky
GitHub
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2e8494f07a
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@ -351,31 +351,45 @@ SPI3_HOST = 2
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////////////////////////////////////////////////////////////////////////////////////////
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#if defined (TFT_PARALLEL_8_BIT)
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#if defined(TFT_DATA_PIN_OFFSET_EN) /* Micky modifies this to select the GPIO control register - 20220701 */
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#define MASK_OFFSET 32
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#define GPIO_CLR_REG GPIO.out1_w1tc.val
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#define GPIO_SET_REG GPIO.out1_w1ts.val
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#else
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#define MASK_OFFSET 0
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#define GPIO_CLR_REG GPIO.out_w1tc
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#define GPIO_SET_REG GPIO.out_w1ts
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#endif
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// Create a bit set lookup table for data bus - wastes 1kbyte of RAM but speeds things up dramatically
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// can then use e.g. GPIO.out_w1ts = set_mask(0xFF); to set data bus to 0xFF
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#define PARALLEL_INIT_TFT_DATA_BUS \
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for (int32_t c = 0; c<256; c++) \
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{ \
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xset_mask[c] = 0; \
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if ( c & 0x01 ) xset_mask[c] |= (1 << TFT_D0); \
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if ( c & 0x02 ) xset_mask[c] |= (1 << TFT_D1); \
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if ( c & 0x04 ) xset_mask[c] |= (1 << TFT_D2); \
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if ( c & 0x08 ) xset_mask[c] |= (1 << TFT_D3); \
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if ( c & 0x10 ) xset_mask[c] |= (1 << TFT_D4); \
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if ( c & 0x20 ) xset_mask[c] |= (1 << TFT_D5); \
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if ( c & 0x40 ) xset_mask[c] |= (1 << TFT_D6); \
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if ( c & 0x80 ) xset_mask[c] |= (1 << TFT_D7); \
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if ( c & 0x01 ) xset_mask[c] |= (1 << (TFT_D0-MASK_OFFSET)); \
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if ( c & 0x02 ) xset_mask[c] |= (1 << (TFT_D1-MASK_OFFSET)); \
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if ( c & 0x04 ) xset_mask[c] |= (1 << (TFT_D2-MASK_OFFSET)); \
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if ( c & 0x08 ) xset_mask[c] |= (1 << (TFT_D3-MASK_OFFSET)); \
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if ( c & 0x10 ) xset_mask[c] |= (1 << (TFT_D4-MASK_OFFSET)); \
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if ( c & 0x20 ) xset_mask[c] |= (1 << (TFT_D5-MASK_OFFSET)); \
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if ( c & 0x40 ) xset_mask[c] |= (1 << (TFT_D6-MASK_OFFSET)); \
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if ( c & 0x80 ) xset_mask[c] |= (1 << (TFT_D7-MASK_OFFSET)); \
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} \
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// Mask for the 8 data bits to set pin directions
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#if defined(TFT_DATA_PIN_OFFSET_EN)
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#define GPIO_DIR_MASK ((1 << (TFT_D0-MASK_OFFSET)) | (1 << (TFT_D1-MASK_OFFSET)) | (1 << (TFT_D2-MASK_OFFSET)) | (1 << (TFT_D3-MASK_OFFSET)) | (1 << (TFT_D4-MASK_OFFSET)) | (1 << (TFT_D5-MASK_OFFSET)) | (1 << (TFT_D6-MASK_OFFSET)) | (1 << (TFT_D7-MASK_OFFSET)))
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#else
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#define GPIO_DIR_MASK ((1 << TFT_D0) | (1 << TFT_D1) | (1 << TFT_D2) | (1 << TFT_D3) | (1 << TFT_D4) | (1 << TFT_D5) | (1 << TFT_D6) | (1 << TFT_D7))
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#endif
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#if (TFT_WR >= 32)
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// Data bits and the write line are cleared sequentially
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#define GPIO_OUT_CLR_MASK (GPIO_DIR_MASK); WR_L
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#elif (TFT_WR >= 0)
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// Data bits and the write line are cleared to 0 in one step (1.25x faster)
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#define GPIO_OUT_CLR_MASK (GPIO_DIR_MASK | (1 << TFT_WR))
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#define GPIO_OUT_CLR_MASK (GPIO_DIR_MASK | (1 << TFT_WR));WR_L
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#else
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#define GPIO_OUT_CLR_MASK
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#endif
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@ -389,7 +403,7 @@ SPI3_HOST = 2
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//*/
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// Write 8 bits to TFT
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#define tft_Write_8(C) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t)(C)); WR_H
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#define tft_Write_8(C) GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t)(C)); WR_H
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#if defined (SSD1963_DRIVER)
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@ -409,33 +423,33 @@ SPI3_HOST = 2
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#define tft_Write_16S(C) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H
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#else
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// Write 16 bits to TFT
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#define tft_Write_16(C) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H; \
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GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 0)); WR_H
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#define tft_Write_16(C) GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 8)); WR_H; \
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GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 0)); WR_H
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// 16 bit write with swapped bytes
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#define tft_Write_16S(C) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 0)); WR_H; \
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GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H
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#define tft_Write_16S(C) GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 0)); WR_H; \
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GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 8)); WR_H
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#endif
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#endif
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// Write 32 bits to TFT
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#define tft_Write_32(C) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 24)); WR_H; \
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GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 16)); WR_H; \
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GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H; \
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GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 0)); WR_H
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#define tft_Write_32(C) GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 24)); WR_H; \
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GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 16)); WR_H; \
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GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 8)); WR_H; \
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GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 0)); WR_H
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// Write two concatenated 16 bit values to TFT
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#define tft_Write_32C(C,D) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H; \
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GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 0)); WR_H; \
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GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((D) >> 8)); WR_H; \
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GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((D) >> 0)); WR_H
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#define tft_Write_32C(C,D) GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 8)); WR_H; \
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GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 0)); WR_H; \
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GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((D) >> 8)); WR_H; \
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GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((D) >> 0)); WR_H
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// Write 16 bit value twice to TFT - used by drawPixel()
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#define tft_Write_32D(C) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H; \
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GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 0)); WR_H; \
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GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H; \
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GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 0)); WR_H
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#define tft_Write_32D(C) GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 8)); WR_H; \
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GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 0)); WR_H; \
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GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 8)); WR_H; \
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GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 0)); WR_H
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// Read pin
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#ifdef TFT_RD
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@ -128,6 +128,8 @@
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//#include <User_Setups/Setup205_ESP32_TouchDown_S3.h> // Setup file for the ESP32 TouchDown S3 based on ILI9488 480 x 320 TFT
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//#include <User_Setups/Setup206_LilyGo_T_Display_S3.h>
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//#include <User_Setups/Setup301_BW16_ST7735.h> // Setup file for Bw16-based boards with ST7735 160 x 80 TFT
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//#include <User_Setups/SetupX_Template.h> // Template file for a setup
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@ -0,0 +1,49 @@
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// ST7789 using 8-bit Parallel
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#define USER_SETUP_ID 206
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#define ST7789_DRIVER
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#define CGRAM_OFFSET
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// #define TFT_RGB_ORDER TFT_RGB // Colour order Red-Green-Blue
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#define TFT_RGB_ORDER TFT_BGR // Colour order Blue-Green-Red
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#define TFT_INVERSION_ON
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// #define TFT_INVERSION_OFF
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#define TFT_PARALLEL_8_BIT
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#define TFT_DATA_PIN_OFFSET_EN /* The ESP32S3 controller is controlled by two registers. \
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Select data pin numbers higher than 32 to enable this option, \
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this macro definition added by Micky -20220701 */
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#define TFT_WIDTH 170
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#define TFT_HEIGHT 320
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#define TFT_DC 7
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#define TFT_RST 5
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#define TFT_WR 8
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#define TFT_RD 9
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#define TFT_D0 39
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#define TFT_D1 40
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#define TFT_D2 41
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#define TFT_D3 42
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#define TFT_D4 45
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#define TFT_D5 46
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#define TFT_D6 47
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#define TFT_D7 48
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#define TFT_BL 38
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#define TFT_BACKLIGHT_ON HIGH
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#define LOAD_GLCD
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#define LOAD_FONT2
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#define LOAD_FONT4
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#define LOAD_FONT6
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#define LOAD_FONT7
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#define LOAD_FONT8
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#define LOAD_GFXFF
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#define SMOOTH_FONT
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