From 2e8494f07a23b186d03980f56c13a6b4ba65ba9a Mon Sep 17 00:00:00 2001 From: Micky <513673326@qq.com> Date: Fri, 6 Jan 2023 23:42:56 +0800 Subject: [PATCH] Added T-DISPLAY-S3 i8080 support for more than 33 data pins (#2296) * Modified the ESP32-S3 I8080 interface's support for data pins above 33 pins. * Added T-DISPLAY-S3 support --- Processors/TFT_eSPI_ESP32_S3.h | 68 +++++++++++++--------- User_Setup_Select.h | 2 + User_Setups/Setup206_LilyGo_T_Display_S3.h | 49 ++++++++++++++++ 3 files changed, 92 insertions(+), 27 deletions(-) create mode 100644 User_Setups/Setup206_LilyGo_T_Display_S3.h diff --git a/Processors/TFT_eSPI_ESP32_S3.h b/Processors/TFT_eSPI_ESP32_S3.h index ec5ad8d..ddee7aa 100644 --- a/Processors/TFT_eSPI_ESP32_S3.h +++ b/Processors/TFT_eSPI_ESP32_S3.h @@ -351,31 +351,45 @@ SPI3_HOST = 2 //////////////////////////////////////////////////////////////////////////////////////// #if defined (TFT_PARALLEL_8_BIT) +#if defined(TFT_DATA_PIN_OFFSET_EN) /* Micky modifies this to select the GPIO control register - 20220701 */ +#define MASK_OFFSET 32 +#define GPIO_CLR_REG GPIO.out1_w1tc.val +#define GPIO_SET_REG GPIO.out1_w1ts.val +#else +#define MASK_OFFSET 0 +#define GPIO_CLR_REG GPIO.out_w1tc +#define GPIO_SET_REG GPIO.out_w1ts +#endif + // Create a bit set lookup table for data bus - wastes 1kbyte of RAM but speeds things up dramatically // can then use e.g. GPIO.out_w1ts = set_mask(0xFF); to set data bus to 0xFF #define PARALLEL_INIT_TFT_DATA_BUS \ for (int32_t c = 0; c<256; c++) \ { \ - xset_mask[c] = 0; \ - if ( c & 0x01 ) xset_mask[c] |= (1 << TFT_D0); \ - if ( c & 0x02 ) xset_mask[c] |= (1 << TFT_D1); \ - if ( c & 0x04 ) xset_mask[c] |= (1 << TFT_D2); \ - if ( c & 0x08 ) xset_mask[c] |= (1 << TFT_D3); \ - if ( c & 0x10 ) xset_mask[c] |= (1 << TFT_D4); \ - if ( c & 0x20 ) xset_mask[c] |= (1 << TFT_D5); \ - if ( c & 0x40 ) xset_mask[c] |= (1 << TFT_D6); \ - if ( c & 0x80 ) xset_mask[c] |= (1 << TFT_D7); \ + xset_mask[c] = 0; \ + if ( c & 0x01 ) xset_mask[c] |= (1 << (TFT_D0-MASK_OFFSET)); \ + if ( c & 0x02 ) xset_mask[c] |= (1 << (TFT_D1-MASK_OFFSET)); \ + if ( c & 0x04 ) xset_mask[c] |= (1 << (TFT_D2-MASK_OFFSET)); \ + if ( c & 0x08 ) xset_mask[c] |= (1 << (TFT_D3-MASK_OFFSET)); \ + if ( c & 0x10 ) xset_mask[c] |= (1 << (TFT_D4-MASK_OFFSET)); \ + if ( c & 0x20 ) xset_mask[c] |= (1 << (TFT_D5-MASK_OFFSET)); \ + if ( c & 0x40 ) xset_mask[c] |= (1 << (TFT_D6-MASK_OFFSET)); \ + if ( c & 0x80 ) xset_mask[c] |= (1 << (TFT_D7-MASK_OFFSET)); \ } \ // Mask for the 8 data bits to set pin directions + #if defined(TFT_DATA_PIN_OFFSET_EN) + #define GPIO_DIR_MASK ((1 << (TFT_D0-MASK_OFFSET)) | (1 << (TFT_D1-MASK_OFFSET)) | (1 << (TFT_D2-MASK_OFFSET)) | (1 << (TFT_D3-MASK_OFFSET)) | (1 << (TFT_D4-MASK_OFFSET)) | (1 << (TFT_D5-MASK_OFFSET)) | (1 << (TFT_D6-MASK_OFFSET)) | (1 << (TFT_D7-MASK_OFFSET))) + #else #define GPIO_DIR_MASK ((1 << TFT_D0) | (1 << TFT_D1) | (1 << TFT_D2) | (1 << TFT_D3) | (1 << TFT_D4) | (1 << TFT_D5) | (1 << TFT_D6) | (1 << TFT_D7)) + #endif #if (TFT_WR >= 32) // Data bits and the write line are cleared sequentially #define GPIO_OUT_CLR_MASK (GPIO_DIR_MASK); WR_L #elif (TFT_WR >= 0) // Data bits and the write line are cleared to 0 in one step (1.25x faster) - #define GPIO_OUT_CLR_MASK (GPIO_DIR_MASK | (1 << TFT_WR)) + #define GPIO_OUT_CLR_MASK (GPIO_DIR_MASK | (1 << TFT_WR));WR_L #else #define GPIO_OUT_CLR_MASK #endif @@ -389,7 +403,7 @@ SPI3_HOST = 2 //*/ // Write 8 bits to TFT - #define tft_Write_8(C) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t)(C)); WR_H + #define tft_Write_8(C) GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t)(C)); WR_H #if defined (SSD1963_DRIVER) @@ -409,33 +423,33 @@ SPI3_HOST = 2 #define tft_Write_16S(C) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H #else // Write 16 bits to TFT - #define tft_Write_16(C) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H; \ - GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 0)); WR_H + #define tft_Write_16(C) GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 8)); WR_H; \ + GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 0)); WR_H // 16 bit write with swapped bytes - #define tft_Write_16S(C) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 0)); WR_H; \ - GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H + #define tft_Write_16S(C) GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 0)); WR_H; \ + GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 8)); WR_H #endif #endif // Write 32 bits to TFT - #define tft_Write_32(C) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 24)); WR_H; \ - GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 16)); WR_H; \ - GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H; \ - GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 0)); WR_H + #define tft_Write_32(C) GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 24)); WR_H; \ + GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 16)); WR_H; \ + GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 8)); WR_H; \ + GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 0)); WR_H // Write two concatenated 16 bit values to TFT - #define tft_Write_32C(C,D) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H; \ - GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 0)); WR_H; \ - GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((D) >> 8)); WR_H; \ - GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((D) >> 0)); WR_H + #define tft_Write_32C(C,D) GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 8)); WR_H; \ + GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 0)); WR_H; \ + GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((D) >> 8)); WR_H; \ + GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((D) >> 0)); WR_H // Write 16 bit value twice to TFT - used by drawPixel() - #define tft_Write_32D(C) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H; \ - GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 0)); WR_H; \ - GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H; \ - GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 0)); WR_H + #define tft_Write_32D(C) GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 8)); WR_H; \ + GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 0)); WR_H; \ + GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 8)); WR_H; \ + GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 0)); WR_H // Read pin #ifdef TFT_RD diff --git a/User_Setup_Select.h b/User_Setup_Select.h index f6da3be..6e65d8c 100644 --- a/User_Setup_Select.h +++ b/User_Setup_Select.h @@ -128,6 +128,8 @@ //#include // Setup file for the ESP32 TouchDown S3 based on ILI9488 480 x 320 TFT +//#include + //#include // Setup file for Bw16-based boards with ST7735 160 x 80 TFT //#include // Template file for a setup diff --git a/User_Setups/Setup206_LilyGo_T_Display_S3.h b/User_Setups/Setup206_LilyGo_T_Display_S3.h new file mode 100644 index 0000000..b4e379c --- /dev/null +++ b/User_Setups/Setup206_LilyGo_T_Display_S3.h @@ -0,0 +1,49 @@ +// ST7789 using 8-bit Parallel + +#define USER_SETUP_ID 206 + +#define ST7789_DRIVER + +#define CGRAM_OFFSET +// #define TFT_RGB_ORDER TFT_RGB // Colour order Red-Green-Blue +#define TFT_RGB_ORDER TFT_BGR // Colour order Blue-Green-Red + +#define TFT_INVERSION_ON +// #define TFT_INVERSION_OFF + +#define TFT_PARALLEL_8_BIT + +#define TFT_DATA_PIN_OFFSET_EN /* The ESP32S3 controller is controlled by two registers. \ + Select data pin numbers higher than 32 to enable this option, \ + this macro definition added by Micky -20220701 */ + +#define TFT_WIDTH 170 +#define TFT_HEIGHT 320 + +#define TFT_DC 7 +#define TFT_RST 5 + +#define TFT_WR 8 +#define TFT_RD 9 + +#define TFT_D0 39 +#define TFT_D1 40 +#define TFT_D2 41 +#define TFT_D3 42 +#define TFT_D4 45 +#define TFT_D5 46 +#define TFT_D6 47 +#define TFT_D7 48 + +#define TFT_BL 38 +#define TFT_BACKLIGHT_ON HIGH + +#define LOAD_GLCD +#define LOAD_FONT2 +#define LOAD_FONT4 +#define LOAD_FONT6 +#define LOAD_FONT7 +#define LOAD_FONT8 +#define LOAD_GFXFF + +#define SMOOTH_FONT \ No newline at end of file