TFT_WR is 8 bit parallel mode can now be allocated to GPIO >31 Note: allocating a GPIO higher than 31 has a small perfomance impact (~1.23x slower) since signle register write with the data mask cannot be performed. |
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| .. | ||
| TFT_eSPI_ESP32.c | ||
| TFT_eSPI_ESP32.h | ||
| TFT_eSPI_ESP8266.c | ||
| TFT_eSPI_ESP8266.h | ||
| TFT_eSPI_Generic.c | ||
| TFT_eSPI_Generic.h | ||
| TFT_eSPI_STM32.c | ||
| TFT_eSPI_STM32.h | ||