807 lines
36 KiB
C
807 lines
36 KiB
C
////////////////////////////////////////////////////
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// TFT_eSPI driver functions for STM32 processors //
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////////////////////////////////////////////////////
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#ifndef _TFT_eSPI_STM32H_
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#define _TFT_eSPI_STM32H_
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// Processor ID reported by getSetup()
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#define PROCESSOR_ID 0x32F
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// Include processor specific header
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// None
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// RPi support not tested - Fast RPi not supported
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// Processor specific code used by SPI bus transaction startWrite and endWrite functions
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#define SET_BUS_WRITE_MODE // Not used
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#define SET_BUS_READ_MODE // Not used
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// SUPPORT_TRANSACTIONS is mandatory for STM32
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#if !defined (SUPPORT_TRANSACTIONS)
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#define SUPPORT_TRANSACTIONS
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#endif
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////////////////////////////////////////////////////////////////////////////////////////
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// Define the parallel bus interface chip pin drive code
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////////////////////////////////////////////////////////////////////////////////////////
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#if defined(TFT_PARALLEL_8_BIT)
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// The STM32 processors can toggle pins fast, TFTs need setup and hold times
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// for writes so here twc can be extended with delays:
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//
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// 0 1 2 3 4 5 Extra high periods
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// TFT_WR ¯|_ _ _ _ _ _ |¯ ¯ ¯ ¯ ¯ ¯ ¯|
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// 5 4 3 2 1 0 Extra low periods
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// xxxx=======================xxxx
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// |<---------- twc --------->|
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// |<- tdst ->|<-- tdht -->|
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//
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// Data is placed bit by bit on bus during period xxxx and TFT_WR driven low
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// Period xxxx depends on D0-D7 pin allocations and bit manipulation needed
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// Data stable during period ===
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// Most TFTs can be "overclocked" and run >2x faster than data sheet figures
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////////////////////////////////////////////////////////////////////////////////////////
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// Write strobe timing setup
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////////////////////////////////////////////////////////////////////////////////////////
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#if defined (ILI9341_DRIVER) || defined (ST7796_DRIVER) // WRX twc spec is 66ns = 15.15MHz
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// Extra write pulse low time (delay for data setup)
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#if defined (STM32F2xx) || defined (STM32F4xx)
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#define WR_TWRL_0 // Tested with STM32F446 - 27.6MHz when WR_TWRH_1 defined
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//#define WR_TWRL_3 // STM32F446 - 15.6MHz when WR_TWRH_3 defined
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#elif defined (STM32F7xx)
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#define WR_TWRL_1 //Tested with STM32F767
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#else
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#define WR_TWRL_5
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#endif
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// Extra write pulse high time (data hold time, delays next write cycle start)
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#if defined (STM32F2xx) || defined (STM32F4xx)
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#define WR_TWRH_1 // Tested with STM32F446
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//#define WR_TWRL_3
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#elif defined (STM32F7xx)
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#define WR_TWRH_1 //Tested with STM32F767
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#else
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#define WR_TWRH_5
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#endif
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#elif defined (ILI9481_DRIVER) // WRX twc spec is 100ns = 10MHz
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// Extra write pulse low time (delay for data setup)
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#if defined (STM32F2xx) || defined (STM32F4xx)
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//#define WR_TWRL_0 // STM32F446 - ~30MHz when WR_TWRH_0 defined
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//#define WR_TWRL_1 // STM32F446 - ~25MHz when WR_TWRH_0 defined
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#define WR_TWRL_2 // STM32F446 - ~20MHz when WR_TWRH_2 defined
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//#define WR_TWRL_3 // STM32F446 - ~16MHz when WR_TWRH_3 defined
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//#define WR_TWRL_4
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//#define WR_TWRL_5 // STM32F446 - ~12MHz when WR_TWRH_5 defined
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#elif defined (STM32F7xx)
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//#define WR_TWRL_0
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//#define WR_TWRL_1
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//#define WR_TWRL_2
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#define WR_TWRL_3
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#else
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//#define WR_TWRH_0 // Fastest
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//#define WR_TWRH_1
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//#define WR_TWRH_2
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#define WR_TWRH_3 // Slowest
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#endif
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// Extra write pulse high time (data hold time, delays next write cycle start)
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#if defined (STM32F2xx) || defined (STM32F4xx)
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//#define WR_TWRH_0
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//#define WR_TWRH_1
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#define WR_TWRH_2
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//#define WR_TWRH_3
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#elif defined (STM32F7xx)
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//#define WR_TWRH_0
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//#define WR_TWRH_1
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//#define WR_TWRH_2
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#define WR_TWRH_3
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//#define WR_TWRH_4
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//#define WR_TWRH_5
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#else
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//#define WR_TWRH_0 // Fastest
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//#define WR_TWRH_1
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//#define WR_TWRH_2
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#define WR_TWRH_3 // Slowest
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#endif
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#else // Default display slow settings
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// Extra write pulse low time (delay for data setup)
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//#define WR_TWRL_0
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//#define WR_TWRL_1
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//#define WR_TWRL_2
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//#define WR_TWRL_3
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//#define WR_TWRL_4
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#define WR_TWRL_5
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// Extra write pulse high time (data hold time, delays next write cycle start)
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//#define WR_TWRH_0
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//#define WR_TWRH_1
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//#define WR_TWRH_2
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//#define WR_TWRH_3
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//#define WR_TWRH_4
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#define WR_TWRH_5
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#endif
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////////////////////////////////////////////////////////////////////////////////////////
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// Macros for all other SPI displays
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////////////////////////////////////////////////////////////////////////////////////////
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#else
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// Global define is _VARIANT_ARDUINO_STM32_, see board package stm32_def.h for specific variants
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#if defined (STM32F2xx) || defined (STM32F4xx) || defined (STM32F7xx)
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#define STM32_DMA // DMA is available with these processors
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// Initialise processor specific SPI and DMA instances - used by init()
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#define INIT_TFT_DATA_BUS spiHal.Instance = SPI1; \
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dmaHal.Instance = DMA2_Stream3
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// The DMA hard-coding for SPI1 is in TFT_eSPI_STM32.c as follows:
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// DMA_CHANNEL_3
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// DMA2_Stream3_IRQn and DMA2_Stream3_IRQHandler()
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#elif defined (STM32F1xx)
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// For Blue Pill and STM32F1xx processors with DMA support
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#define STM32_DMA // DMA is available with these processors
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#define INIT_TFT_DATA_BUS spiHal.Instance = SPI1; \
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dmaHal.Instance = DMA1_Channel3
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#else
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// For STM32 processor with no implemented DMA support (yet)
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#define INIT_TFT_DATA_BUS spiHal.Instance = SPI1
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#endif
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#endif
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#ifdef STM32_DMA
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// Code to check if DMA is busy, used by SPI DMA + transaction + endWrite functions
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#define DMA_BUSY_CHECK { if (DMA_Enabled) while(dmaBusy()); }
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#else
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#define DMA_BUSY_CHECK
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#endif
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// If smooth fonts are enabled the filing system may need to be loaded
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#ifdef SMOOTH_FONT
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// Call up the filing system for the anti-aliased fonts <<<==== TODO
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//#define FS_NO_GLOBALS
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//#include <FS.h>
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#endif // end of parallel/SPI selection
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////////////////////////////////////////////////////////////////////////////////////////
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// Define the DC (TFT Data/Command or Register Select (RS))pin drive code
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////////////////////////////////////////////////////////////////////////////////////////
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#if !defined (TFT_DC) || (TFT_DC < 0)
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#define DC_C // No macro allocated so it generates no code
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#define DC_D // No macro allocated so it generates no code
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#else
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// Convert Arduino pin reference Dn or STM pin reference PXn to hardware port and mask
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#define DC_PIN_NAME digitalPinToPinName(TFT_DC)
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#define DC_PORT get_GPIO_Port(STM_PORT(DC_PIN_NAME))
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#define DC_PIN_MASK STM_LL_GPIO_PIN(DC_PIN_NAME)
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// Use bit set reset register
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#define DC_C DC_PORT->BSRR = DC_PIN_MASK<<16
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#define DC_D DC_PORT->BSRR = DC_PIN_MASK
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#endif
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////////////////////////////////////////////////////////////////////////////////////////
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// Define the CS (TFT chip select) pin drive code
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////////////////////////////////////////////////////////////////////////////////////////
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#if !defined (TFT_CS) || (TFT_CS < 0)
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#define CS_L // No macro allocated so it generates no code
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#define CS_H // No macro allocated so it generates no code
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#else
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// Convert Arduino pin reference Dx or STM pin reference PXn to hardware port and mask
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#define CS_PIN_NAME digitalPinToPinName(TFT_CS)
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#define CS_PORT get_GPIO_Port(STM_PORT(CS_PIN_NAME))
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#define CS_PIN_MASK STM_LL_GPIO_PIN(CS_PIN_NAME)
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// Use bit set reset register
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#define CS_L CS_PORT->BSRR = CS_PIN_MASK<<16
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#define CS_H CS_PORT->BSRR = CS_PIN_MASK
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#endif
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////////////////////////////////////////////////////////////////////////////////////////
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// Define the RD (TFT Read) pin drive code
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////////////////////////////////////////////////////////////////////////////////////////
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#ifdef TFT_RD
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// Convert Arduino pin reference Dx or STM pin reference PXn to hardware port and mask
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#define RD_PIN_NAME digitalPinToPinName(TFT_RD)
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#define RD_PORT get_GPIO_Port(STM_PORT(RD_PIN_NAME))
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#define RD_PIN_MASK STM_LL_GPIO_PIN(RD_PIN_NAME)
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// Use bit set reset register
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#define RD_L RD_PORT->BSRR = RD_PIN_MASK<<16
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#define RD_H RD_PORT->BSRR = RD_PIN_MASK
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#endif
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////////////////////////////////////////////////////////////////////////////////////////
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// Define the WR (TFT Write) pin drive code
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////////////////////////////////////////////////////////////////////////////////////////
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#ifdef TFT_WR
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// Convert Arduino pin reference Dx or STM pin reference PXn to hardware port and mask
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#define WR_PIN_NAME digitalPinToPinName(TFT_WR)
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#define WR_PORT get_GPIO_Port(STM_PORT(WR_PIN_NAME))
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#define WR_PIN_MASK STM_LL_GPIO_PIN(WR_PIN_NAME)
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// Use bit set reset register
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#define WR_L WR_PORT->BSRR = WR_PIN_MASK<<16
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#ifdef ILI9341_DRIVER
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#define WR_H WR_PORT->BSRR = WR_PIN_MASK
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#else
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#define WR_H WR_PORT->BSRR = WR_PIN_MASK
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#endif
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#endif
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////////////////////////////////////////////////////////////////////////////////////////
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// Define the touch screen chip select pin drive code
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////////////////////////////////////////////////////////////////////////////////////////
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#if !defined (TOUCH_CS) || (TOUCH_CS < 0)
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#define T_CS_L // No macro allocated so it generates no code
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#define T_CS_H // No macro allocated so it generates no code
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#else
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// Speed is not important for this signal
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#define T_CS_L digitalWrite(TOUCH_CS, LOW)
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#define T_CS_H digitalWrite(TOUCH_CS, HIGH)
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#endif
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////////////////////////////////////////////////////////////////////////////////////////
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// Make sure TFT_MISO is defined if not used to avoid an error message
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////////////////////////////////////////////////////////////////////////////////////////
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#if !defined (TFT_PARALLEL_8_BIT)
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#ifndef TFT_MISO
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#define TFT_MISO -1
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#endif
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#endif
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////////////////////////////////////////////////////////////////////////////////////////
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// Define the parallel bus interface chip pin drive code
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////////////////////////////////////////////////////////////////////////////////////////
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#if defined (TFT_PARALLEL_8_BIT)
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// Mask for the 8 data bits to set pin directions (not used)
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#define dir_mask 0
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#define CONSTRUCTOR_INIT_TFT_DATA_BUS // None
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#define INIT_TFT_DATA_BUS // Setup built into TFT_eSPI.cpp
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////////////////////////////////////////////////////////////////////////////////////////
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// Define the TFT_WR drive cycle timing
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////////////////////////////////////////////////////////////////////////////////////////
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// Write low extra setup time
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#if defined WR_TWRL_0
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#define WR_TWRL
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#elif defined WR_TWRL_1 // 1 extra low period
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#define WR_TWRL WR_L
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#elif defined WR_TWRL_2 // 2 extra low periods
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#define WR_TWRL WR_L; WR_L
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#elif defined WR_TWRL_3 // 3 extra low periods
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#define WR_TWRL WR_L; WR_L; WR_L
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#elif defined WR_TWRL_4 // 4 extra low periods
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#define WR_TWRL WR_L; WR_L; WR_L; WR_L
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#elif defined WR_TWRL_5 // 5 extra low periods
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#define WR_TWRL WR_L; WR_L; WR_L; WR_L; WR_L
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#endif
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// Write high extra hold time
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#if defined WR_TWRH_0
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#define WR_TWRH WR_H
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#elif defined WR_TWRH_1 // 1 extra high period
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#define WR_TWRH WR_H; WR_H
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#elif defined WR_TWRH_2 // 2 extra high periods
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#define WR_TWRH WR_H; WR_H; WR_H
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#elif defined WR_TWRH_3 // 3 extra high periods
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#define WR_TWRH WR_H; WR_H; WR_H; WR_H
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#elif defined WR_TWRH_4 // 4 extra high periods
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#define WR_TWRH WR_H; WR_H; WR_H; WR_H; WR_H
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#elif defined WR_TWRH_5 // 5 extra high periods
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#define WR_TWRH WR_H; WR_H; WR_H; WR_H; WR_H; WR_H
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#endif
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#define WR_STB WR_TWRL; WR_TWRH // Rising edge write strobe
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////////////////////////////////////////////////////////////////////////////////////////
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// Nucleo 64: hard-coded pins
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////////////////////////////////////////////////////////////////////////////////////////
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#ifdef NUCLEO_64_TFT
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// Nucleo 64 boards use the same ports/pins
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#define D0_PIN_BIT LL_GPIO_PIN_9
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#define D1_PIN_BIT LL_GPIO_PIN_7
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#define D2_PIN_BIT LL_GPIO_PIN_10
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#define D3_PIN_BIT LL_GPIO_PIN_3
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#define D4_PIN_BIT LL_GPIO_PIN_5
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#define D5_PIN_BIT LL_GPIO_PIN_4
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#define D6_PIN_BIT LL_GPIO_PIN_10
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#define D7_PIN_BIT LL_GPIO_PIN_8
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// Ports associated with pins - better than get_GPIO_Port() which seems to be slow...
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#define D0_PIN_PORT GPIOA
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#define D1_PIN_PORT GPIOC
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#define D2_PIN_PORT GPIOA
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#define D3_PIN_PORT GPIOB
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#define D4_PIN_PORT GPIOB
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#define D5_PIN_PORT GPIOB
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#define D6_PIN_PORT GPIOB
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#define D7_PIN_PORT GPIOA
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// Pin masks for set/clear
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#define D0_PIN_MASK (1UL<< 9) // Set/clear mask for PA9
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#define D1_PIN_MASK (1UL<< 7) // Set/clear mask for PC7
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#define D2_PIN_MASK (1UL<<10) // Set/clear mask for PA10
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#define D3_PIN_MASK (1UL<< 3) // Set/clear mask for PB3
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#define D4_PIN_MASK (1UL<< 5) // Set/clear mask for PB5
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#define D5_PIN_MASK (1UL<< 4) // Set/clear mask for PB4
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#define D6_PIN_MASK (1UL<<10) // Set/clear mask for PB10
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#define D7_PIN_MASK (1UL<< 8) // Set/clear mask for PA8
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// Create bit set/reset mask based on LS byte of value B
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#define D0_BSR_MASK(B) ((D0_PIN_MASK<<16)>>(((B)<< 4)&0x10))
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#define D1_BSR_MASK(B) ((D1_PIN_MASK<<16)>>(((B)<< 3)&0x10))
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#define D2_BSR_MASK(B) ((D2_PIN_MASK<<16)>>(((B)<< 2)&0x10))
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#define D3_BSR_MASK(B) ((D3_PIN_MASK<<16)>>(((B)<< 1)&0x10))
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#define D4_BSR_MASK(B) ((D4_PIN_MASK<<16)>>(((B)<< 0)&0x10))
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#define D5_BSR_MASK(B) ((D5_PIN_MASK<<16)>>(((B)>> 1)&0x10))
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#define D6_BSR_MASK(B) ((D6_PIN_MASK<<16)>>(((B)>> 2)&0x10))
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#define D7_BSR_MASK(B) ((D7_PIN_MASK<<16)>>(((B)>> 3)&0x10))
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// Create bit set/reset mask for top byte of 16 bit value B
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#define D8_BSR_MASK(B) ((D0_PIN_MASK<<16)>>(((B)>> 4)&0x10))
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#define D9_BSR_MASK(B) ((D1_PIN_MASK<<16)>>(((B)>> 5)&0x10))
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#define D10_BSR_MASK(B) ((D2_PIN_MASK<<16)>>(((B)>> 6)&0x10))
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#define D11_BSR_MASK(B) ((D3_PIN_MASK<<16)>>(((B)>> 7)&0x10))
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#define D12_BSR_MASK(B) ((D4_PIN_MASK<<16)>>(((B)>> 8)&0x10))
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#define D13_BSR_MASK(B) ((D5_PIN_MASK<<16)>>(((B)>> 9)&0x10))
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#define D14_BSR_MASK(B) ((D6_PIN_MASK<<16)>>(((B)>>10)&0x10))
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#define D15_BSR_MASK(B) ((D7_PIN_MASK<<16)>>(((B)>>11)&0x10))
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// Write 8 bits to TFT
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#define tft_Write_8(C) GPIOA->BSRR = D0_BSR_MASK(C) | D2_BSR_MASK(C) | D7_BSR_MASK(C); \
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WR_L; \
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GPIOC->BSRR = D1_BSR_MASK(C); \
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GPIOB->BSRR = D3_BSR_MASK(C) | D4_BSR_MASK(C) | D5_BSR_MASK(C) | D6_BSR_MASK(C); \
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WR_STB // Need to slow down strobe
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// Write 16 bits to TFT
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#define tft_Write_16(C) GPIOA->BSRR = D8_BSR_MASK(C) | D10_BSR_MASK(C) | D15_BSR_MASK(C); \
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WR_L; \
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GPIOC->BSRR = D9_BSR_MASK(C); \
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GPIOB->BSRR = D11_BSR_MASK(C) | D12_BSR_MASK(C) | D13_BSR_MASK(C) | D14_BSR_MASK(C); \
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WR_STB; \
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GPIOA->BSRR = D0_BSR_MASK(C) | D2_BSR_MASK(C) | D7_BSR_MASK(C); \
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WR_L; \
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GPIOC->BSRR = D1_BSR_MASK(C); \
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GPIOB->BSRR = D3_BSR_MASK(C) | D4_BSR_MASK(C) | D5_BSR_MASK(C) | D6_BSR_MASK(C); \
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WR_STB // Need to slow down strobe
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// 16 bit write with swapped bytes
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#define tft_Write_16S(C) GPIOA->BSRR = D0_BSR_MASK(C) | D2_BSR_MASK(C) | D7_BSR_MASK(C); \
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WR_L; \
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GPIOC->BSRR = D1_BSR_MASK(C); \
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GPIOB->BSRR = D3_BSR_MASK(C) | D4_BSR_MASK(C) | D5_BSR_MASK(C) | D6_BSR_MASK(C); \
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WR_STB; \
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GPIOA->BSRR = D8_BSR_MASK(C) | D10_BSR_MASK(C) | D15_BSR_MASK(C); \
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WR_L; \
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GPIOC->BSRR = D9_BSR_MASK(C); \
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GPIOB->BSRR = D11_BSR_MASK(C) | D12_BSR_MASK(C) | D13_BSR_MASK(C) | D14_BSR_MASK(C); \
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WR_STB
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// Read a data bit
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#define RD_TFT_D0 (((GPIOA->IDR)&(D0_PIN_MASK))>>( 9-0)) // Read pin PA9
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#define RD_TFT_D1 (((GPIOC->IDR)&(D1_PIN_MASK))>>( 7-1)) // Read pin PC7
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#define RD_TFT_D2 (((GPIOA->IDR)&(D2_PIN_MASK))>>(10-2)) // Read pin PA10
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#define RD_TFT_D3 (((GPIOB->IDR)&(D3_PIN_MASK))>>( 3-3)) // Read pin PB3
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#define RD_TFT_D4 (((GPIOB->IDR)&(D4_PIN_MASK))>>( 5-4)) // Read pin PB5
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#define RD_TFT_D5 (((GPIOB->IDR)&(D5_PIN_MASK))<<(-4+5)) // Read pin PB4
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#define RD_TFT_D6 (((GPIOB->IDR)&(D6_PIN_MASK))>>(10-6)) // Read pin PB10
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#define RD_TFT_D7 (((GPIOA->IDR)&(D7_PIN_MASK))>>( 8-7)) // Read pin PA8
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////////////////////////////////////////////////////////////////////////////////////////
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// Nucleo 144: hard-coded pins
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////////////////////////////////////////////////////////////////////////////////////////
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#elif defined (NUCLEO_144_TFT)
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#if !defined (STM32H7xx)
|
|
// Nucleo 144 boards use the same ports/pins
|
|
#define D0_PIN_BIT LL_GPIO_PIN_12
|
|
#define D1_PIN_BIT LL_GPIO_PIN_15
|
|
#define D2_PIN_BIT LL_GPIO_PIN_15
|
|
#define D3_PIN_BIT LL_GPIO_PIN_13
|
|
#define D4_PIN_BIT LL_GPIO_PIN_14
|
|
#define D5_PIN_BIT LL_GPIO_PIN_11
|
|
#define D6_PIN_BIT LL_GPIO_PIN_9
|
|
#define D7_PIN_BIT LL_GPIO_PIN_13
|
|
|
|
// Ports associated with pins - get_GPIO_Port() seems to be slow...
|
|
#define D0_PIN_PORT GPIOF
|
|
#define D1_PIN_PORT GPIOD
|
|
#define D2_PIN_PORT GPIOF
|
|
#define D3_PIN_PORT GPIOE
|
|
#define D4_PIN_PORT GPIOF
|
|
#define D5_PIN_PORT GPIOE
|
|
#define D6_PIN_PORT GPIOE
|
|
#define D7_PIN_PORT GPIOF
|
|
|
|
// Pin masks for set/clear
|
|
#define D0_PIN_MASK (1UL<<12) // Set/clear mask for PF12 PF3
|
|
#define D1_PIN_MASK (1UL<<15) // Set/clear mask for PD15
|
|
#define D2_PIN_MASK (1UL<<15) // Set/clear mask for PF15 PG14
|
|
#define D3_PIN_MASK (1UL<<13) // Set/clear mask for PE13
|
|
#define D4_PIN_MASK (1UL<<14) // Set/clear mask for PF14
|
|
#define D5_PIN_MASK (1UL<<11) // Set/clear mask for PE11
|
|
#define D6_PIN_MASK (1UL<< 9) // Set/clear mask for PE9
|
|
#define D7_PIN_MASK (1UL<<13) // Set/clear mask for PF13 PG12
|
|
|
|
// Create bit set/reset mask based on LS byte of value B
|
|
#define D0_BSR_MASK(B) ((D0_PIN_MASK<<16)>>(((B)<< 4)&0x10))
|
|
#define D1_BSR_MASK(B) ((D1_PIN_MASK<<16)>>(((B)<< 3)&0x10))
|
|
#define D2_BSR_MASK(B) ((D2_PIN_MASK<<16)>>(((B)<< 2)&0x10))
|
|
#define D3_BSR_MASK(B) ((D3_PIN_MASK<<16)>>(((B)<< 1)&0x10))
|
|
#define D4_BSR_MASK(B) ((D4_PIN_MASK<<16)>>(((B)<< 0)&0x10))
|
|
#define D5_BSR_MASK(B) ((D5_PIN_MASK<<16)>>(((B)>> 1)&0x10))
|
|
#define D6_BSR_MASK(B) ((D6_PIN_MASK<<16)>>(((B)>> 2)&0x10))
|
|
#define D7_BSR_MASK(B) ((D7_PIN_MASK<<16)>>(((B)>> 3)&0x10))
|
|
// Create bit set/reset mask for top byte of 16 bit value B
|
|
#define D8_BSR_MASK(B) ((D0_PIN_MASK<<16)>>(((B)>> 4)&0x10))
|
|
#define D9_BSR_MASK(B) ((D1_PIN_MASK<<16)>>(((B)>> 5)&0x10))
|
|
#define D10_BSR_MASK(B) ((D2_PIN_MASK<<16)>>(((B)>> 6)&0x10))
|
|
#define D11_BSR_MASK(B) ((D3_PIN_MASK<<16)>>(((B)>> 7)&0x10))
|
|
#define D12_BSR_MASK(B) ((D4_PIN_MASK<<16)>>(((B)>> 8)&0x10))
|
|
#define D13_BSR_MASK(B) ((D5_PIN_MASK<<16)>>(((B)>> 9)&0x10))
|
|
#define D14_BSR_MASK(B) ((D6_PIN_MASK<<16)>>(((B)>>10)&0x10))
|
|
#define D15_BSR_MASK(B) ((D7_PIN_MASK<<16)>>(((B)>>11)&0x10))
|
|
|
|
|
|
// Write 8 bits to TFT
|
|
#define tft_Write_8(C) GPIOF->BSRR = D0_BSR_MASK(C) | D2_BSR_MASK(C) | D4_BSR_MASK(C) | D7_BSR_MASK(C); \
|
|
WR_L; \
|
|
GPIOD->BSRR = D1_BSR_MASK(C); \
|
|
GPIOE->BSRR = D3_BSR_MASK(C) | D5_BSR_MASK(C) | D6_BSR_MASK(C); \
|
|
WR_STB
|
|
|
|
// Write 16 bits to TFT
|
|
#define tft_Write_16(C) GPIOF->BSRR = D8_BSR_MASK(C) | D10_BSR_MASK(C) | D12_BSR_MASK(C) | D15_BSR_MASK(C); \
|
|
WR_L; \
|
|
GPIOD->BSRR = D9_BSR_MASK(C); \
|
|
GPIOE->BSRR = D11_BSR_MASK(C) | D13_BSR_MASK(C) | D14_BSR_MASK(C); \
|
|
WR_STB;\
|
|
GPIOF->BSRR = D0_BSR_MASK(C) | D2_BSR_MASK(C) | D4_BSR_MASK(C) | D7_BSR_MASK(C); \
|
|
WR_L; \
|
|
GPIOD->BSRR = D1_BSR_MASK(C); \
|
|
GPIOE->BSRR = D3_BSR_MASK(C) | D5_BSR_MASK(C) | D6_BSR_MASK(C); \
|
|
WR_STB
|
|
|
|
// 16 bit write with swapped bytes
|
|
#define tft_Write_16S(C) GPIOF->BSRR = D0_BSR_MASK(C) | D2_BSR_MASK(C) | D4_BSR_MASK(C) | D7_BSR_MASK(C); \
|
|
WR_L; \
|
|
GPIOD->BSRR = D1_BSR_MASK(C); \
|
|
GPIOE->BSRR = D3_BSR_MASK(C) | D5_BSR_MASK(C) | D6_BSR_MASK(C); \
|
|
WR_STB; \
|
|
GPIOF->BSRR = D8_BSR_MASK(C) | D10_BSR_MASK(C) | D12_BSR_MASK(C) | D15_BSR_MASK(C); \
|
|
WR_L; \
|
|
GPIOD->BSRR = D9_BSR_MASK(C); \
|
|
GPIOE->BSRR = D11_BSR_MASK(C) | D13_BSR_MASK(C) | D14_BSR_MASK(C); \
|
|
WR_STB
|
|
|
|
// Read a data bit
|
|
#define RD_TFT_D0 (((GPIOF->IDR)&(D0_PIN_MASK))>>(12-0)) // Read pin PF12
|
|
#define RD_TFT_D1 (((GPIOD->IDR)&(D1_PIN_MASK))>>(15-1)) // Read pin PD15
|
|
#define RD_TFT_D2 (((GPIOF->IDR)&(D2_PIN_MASK))>>(15-2)) // Read pin PF15
|
|
#define RD_TFT_D3 (((GPIOE->IDR)&(D3_PIN_MASK))>>(13-3)) // Read pin PE13
|
|
#define RD_TFT_D4 (((GPIOF->IDR)&(D4_PIN_MASK))>>(14-4)) // Read pin PF14
|
|
#define RD_TFT_D5 (((GPIOE->IDR)&(D5_PIN_MASK))>>(11-5)) // Read pin PE11
|
|
#define RD_TFT_D6 (((GPIOE->IDR)&(D6_PIN_MASK))>>( 9-6)) // Read pin PE9
|
|
#define RD_TFT_D7 (((GPIOF->IDR)&(D7_PIN_MASK))>>(13-7)) // Read pin PF13
|
|
|
|
#else
|
|
|
|
// Test setup for STM32H743 - starts to run, slow and then crashes! Board support bug?
|
|
|
|
// Nucleo 144 boards use the same ports/pins
|
|
#define D0_PIN_BIT LL_GPIO_PIN_3
|
|
#define D1_PIN_BIT LL_GPIO_PIN_15
|
|
#define D2_PIN_BIT LL_GPIO_PIN_14
|
|
#define D3_PIN_BIT LL_GPIO_PIN_13
|
|
#define D4_PIN_BIT LL_GPIO_PIN_14
|
|
#define D5_PIN_BIT LL_GPIO_PIN_11
|
|
#define D6_PIN_BIT LL_GPIO_PIN_9
|
|
#define D7_PIN_BIT LL_GPIO_PIN_12
|
|
|
|
// Ports associated with pins - get_GPIO_Port() seems to be slow...
|
|
#define D0_PIN_PORT GPIOF
|
|
#define D1_PIN_PORT GPIOD
|
|
#define D2_PIN_PORT GPIOG
|
|
#define D3_PIN_PORT GPIOE
|
|
#define D4_PIN_PORT GPIOE
|
|
#define D5_PIN_PORT GPIOE
|
|
#define D6_PIN_PORT GPIOE
|
|
#define D7_PIN_PORT GPIOG
|
|
|
|
// Pin masks for set/clear
|
|
#define D0_PIN_MASK (1UL<< 3) // Set/clear mask for PF3
|
|
#define D1_PIN_MASK (1UL<<15) // Set/clear mask for PD15
|
|
#define D2_PIN_MASK (1UL<<14) // Set/clear mask for PG14
|
|
#define D3_PIN_MASK (1UL<<13) // Set/clear mask for PE13
|
|
#define D4_PIN_MASK (1UL<<14) // Set/clear mask for PE14
|
|
#define D5_PIN_MASK (1UL<<11) // Set/clear mask for PE11
|
|
#define D6_PIN_MASK (1UL<< 9) // Set/clear mask for PE9
|
|
#define D7_PIN_MASK (1UL<<12) // Set/clear mask for PG12
|
|
|
|
// Create bit set/reset mask based on LS byte of value B
|
|
#define D0_BSR_MASK(B) ((D0_PIN_MASK<<16)>>(((B)<< 4)&0x10))
|
|
#define D1_BSR_MASK(B) ((D1_PIN_MASK<<16)>>(((B)<< 3)&0x10))
|
|
#define D2_BSR_MASK(B) ((D2_PIN_MASK<<16)>>(((B)<< 2)&0x10))
|
|
#define D3_BSR_MASK(B) ((D3_PIN_MASK<<16)>>(((B)<< 1)&0x10))
|
|
#define D4_BSR_MASK(B) ((D4_PIN_MASK<<16)>>(((B)<< 0)&0x10))
|
|
#define D5_BSR_MASK(B) ((D5_PIN_MASK<<16)>>(((B)>> 1)&0x10))
|
|
#define D6_BSR_MASK(B) ((D6_PIN_MASK<<16)>>(((B)>> 2)&0x10))
|
|
#define D7_BSR_MASK(B) ((D7_PIN_MASK<<16)>>(((B)>> 3)&0x10))
|
|
// Create bit set/reset mask for top byte of 16 bit value B
|
|
#define D8_BSR_MASK(B) ((D0_PIN_MASK<<16)>>(((B)>> 4)&0x10))
|
|
#define D9_BSR_MASK(B) ((D1_PIN_MASK<<16)>>(((B)>> 5)&0x10))
|
|
#define D10_BSR_MASK(B) ((D2_PIN_MASK<<16)>>(((B)>> 6)&0x10))
|
|
#define D11_BSR_MASK(B) ((D3_PIN_MASK<<16)>>(((B)>> 7)&0x10))
|
|
#define D12_BSR_MASK(B) ((D4_PIN_MASK<<16)>>(((B)>> 8)&0x10))
|
|
#define D13_BSR_MASK(B) ((D5_PIN_MASK<<16)>>(((B)>> 9)&0x10))
|
|
#define D14_BSR_MASK(B) ((D6_PIN_MASK<<16)>>(((B)>>10)&0x10))
|
|
#define D15_BSR_MASK(B) ((D7_PIN_MASK<<16)>>(((B)>>11)&0x10))
|
|
|
|
|
|
// Write 8 bits to TFT
|
|
#define tft_Write_8(C) GPIOF->BSRR = D0_BSR_MASK(C); \
|
|
GPIOG->BSRR = D2_BSR_MASK(C) | D7_BSR_MASK(C); \
|
|
WR_L; \
|
|
GPIOD->BSRR = D1_BSR_MASK(C); \
|
|
GPIOE->BSRR = D3_BSR_MASK(C) | D4_BSR_MASK(C) | D5_BSR_MASK(C) | D6_BSR_MASK(C); \
|
|
WR_STB
|
|
|
|
// Write 16 bits to TFT
|
|
#define tft_Write_16(C) GPIOF->BSRR = D8_BSR_MASK(C); \
|
|
GPIOG->BSRR = D10_BSR_MASK(C) | D15_BSR_MASK(C); \
|
|
WR_L; \
|
|
GPIOD->BSRR = D9_BSR_MASK(C); \
|
|
GPIOE->BSRR = D11_BSR_MASK(C) | D12_BSR_MASK(C) | D13_BSR_MASK(C) | D14_BSR_MASK(C); \
|
|
WR_STB;\
|
|
GPIOF->BSRR = D0_BSR_MASK(C); \
|
|
GPIOG->BSRR = D2_BSR_MASK(C) | D7_BSR_MASK(C); \
|
|
WR_L; \
|
|
GPIOD->BSRR = D1_BSR_MASK(C); \
|
|
GPIOE->BSRR = D3_BSR_MASK(C) | D4_BSR_MASK(C) | D5_BSR_MASK(C) | D6_BSR_MASK(C); \
|
|
WR_STB
|
|
|
|
// 16 bit write with swapped bytes
|
|
#define tft_Write_16S(C) GPIOF->BSRR = D0_BSR_MASK(C); \
|
|
GPIOG->BSRR = D2_BSR_MASK(C) | D7_BSR_MASK(C); \
|
|
WR_L; \
|
|
GPIOD->BSRR = D1_BSR_MASK(C); \
|
|
GPIOE->BSRR = D3_BSR_MASK(C) | D4_BSR_MASK(C) | D5_BSR_MASK(C) | D6_BSR_MASK(C); \
|
|
WR_STB; \
|
|
GPIOF->BSRR = D8_BSR_MASK(C); \
|
|
GPIOG->BSRR = D10_BSR_MASK(C) | D15_BSR_MASK(C); \
|
|
WR_L; \
|
|
GPIOD->BSRR = D9_BSR_MASK(C); \
|
|
GPIOE->BSRR = D11_BSR_MASK(C) | D12_BSR_MASK(C) | D13_BSR_MASK(C) | D14_BSR_MASK(C); \
|
|
WR_STB
|
|
|
|
// Read a data bit
|
|
#define RD_TFT_D0 (((GPIOF->IDR)&(D0_PIN_MASK))>>( 3-0)) // Read pin PF3
|
|
#define RD_TFT_D1 (((GPIOD->IDR)&(D1_PIN_MASK))>>(15-1)) // Read pin PD15
|
|
#define RD_TFT_D2 (((GPIOG->IDR)&(D2_PIN_MASK))>>(14-2)) // Read pin PG14
|
|
#define RD_TFT_D3 (((GPIOE->IDR)&(D3_PIN_MASK))>>(13-3)) // Read pin PE13
|
|
#define RD_TFT_D4 (((GPIOE->IDR)&(D4_PIN_MASK))>>(14-4)) // Read pin PE14
|
|
#define RD_TFT_D5 (((GPIOE->IDR)&(D5_PIN_MASK))>>(11-5)) // Read pin PE11
|
|
#define RD_TFT_D6 (((GPIOE->IDR)&(D6_PIN_MASK))>>( 9-6)) // Read pin PE9
|
|
#define RD_TFT_D7 (((GPIOG->IDR)&(D7_PIN_MASK))>>(12-7)) // Read pin PG12
|
|
#endif
|
|
////////////////////////////////////////////////////////////////////////////////////////
|
|
// Support for other STM32 boards (not optimised!)
|
|
////////////////////////////////////////////////////////////////////////////////////////
|
|
#else
|
|
|
|
// This will work with any STM32 to parallel TFT pin mapping but will be slower
|
|
|
|
// Convert Arduino pin reference Dx or STM pin reference PXn to hardware port and mask
|
|
#define D0_PIN_NAME digitalPinToPinName(TFT_D0)
|
|
#ifndef D0_PORT
|
|
#define D0_PORT get_GPIO_Port(STM_PORT(D0_PIN_NAME))
|
|
#endif
|
|
#define D0_PIN_MASK (const uint16_t)STM_LL_GPIO_PIN(D0_PIN_NAME)<<16
|
|
// Use bit set reset register
|
|
#define D0_BSR(B) D0_PORT->BSRR = (D0_PIN_MASK)>>(B)
|
|
|
|
// Convert Arduino pin reference Dx or STM pin reference PXn to hardware port and mask
|
|
#define D1_PIN_NAME digitalPinToPinName(TFT_D1)
|
|
#ifndef D1_PORT
|
|
#define D1_PORT get_GPIO_Port(STM_PORT(D1_PIN_NAME))
|
|
#endif
|
|
#define D1_PIN_MASK STM_LL_GPIO_PIN(D1_PIN_NAME)<<16
|
|
// Use bit set reset register
|
|
#define D1_BSR(B) D1_PORT->BSRR = D1_PIN_MASK>>(B)
|
|
|
|
// Convert Arduino pin reference Dx or STM pin reference PXn to hardware port and mask
|
|
#define D2_PIN_NAME digitalPinToPinName(TFT_D2)
|
|
#ifndef D2_PORT
|
|
#define D2_PORT get_GPIO_Port(STM_PORT(D2_PIN_NAME))
|
|
#endif
|
|
#define D2_PIN_MASK (const uint16_t)STM_LL_GPIO_PIN(D2_PIN_NAME)<<16
|
|
// Use bit set reset register
|
|
#define D2_BSR(B) D2_PORT->BSRR = D2_PIN_MASK>>(B)
|
|
|
|
// Convert Arduino pin reference Dx or STM pin reference PXn to hardware port and mask
|
|
#define D3_PIN_NAME digitalPinToPinName(TFT_D3)
|
|
#ifndef D3_PORT
|
|
#define D3_PORT get_GPIO_Port(STM_PORT(D3_PIN_NAME))
|
|
#endif
|
|
#define D3_PIN_MASK (const uint16_t)STM_LL_GPIO_PIN(D3_PIN_NAME)<<16
|
|
// Use bit set reset register
|
|
#define D3_BSR(B) D3_PORT->BSRR = D3_PIN_MASK>>(B)
|
|
|
|
// Convert Arduino pin reference Dx or STM pin reference PXn to hardware port and mask
|
|
#define D4_PIN_NAME digitalPinToPinName(TFT_D4)
|
|
#ifndef D4_PORT
|
|
#define D4_PORT get_GPIO_Port(STM_PORT(D4_PIN_NAME))
|
|
#endif
|
|
#define D4_PIN_MASK (const uint16_t)STM_LL_GPIO_PIN(D4_PIN_NAME)<<16
|
|
// Use bit set reset register
|
|
#define D4_BSR(B) D4_PORT->BSRR = D4_PIN_MASK>>(B)
|
|
|
|
// Convert Arduino pin reference Dx or STM pin reference PXn to hardware port and mask
|
|
#define D5_PIN_NAME digitalPinToPinName(TFT_D5)
|
|
#ifndef D5_PORT
|
|
#define D5_PORT get_GPIO_Port(STM_PORT(D5_PIN_NAME))
|
|
#endif
|
|
#define D5_PIN_MASK (const uint16_t)STM_LL_GPIO_PIN(D5_PIN_NAME)<<16
|
|
// Use bit set reset register
|
|
#define D5_BSR(B) D5_PORT->BSRR = D5_PIN_MASK>>(B)
|
|
|
|
// Convert Arduino pin reference Dx or STM pin reference PXn to hardware port and mask
|
|
#define D6_PIN_NAME digitalPinToPinName(TFT_D6)
|
|
#ifndef D6_PORT
|
|
#define D6_PORT get_GPIO_Port(STM_PORT(D6_PIN_NAME))
|
|
#endif
|
|
#define D6_PIN_MASK (const uint16_t)STM_LL_GPIO_PIN(D6_PIN_NAME)<<16
|
|
// Use bit set reset register
|
|
#define D6_BSR(B) D6_PORT->BSRR = D6_PIN_MASK>>(B)
|
|
|
|
// Convert Arduino pin reference Dx or STM pin reference PXn to hardware port and mask
|
|
#define D7_PIN_NAME digitalPinToPinName(TFT_D7)
|
|
#ifndef D7_PORT
|
|
#define D7_PORT get_GPIO_Port(STM_PORT(D7_PIN_NAME))
|
|
#endif
|
|
#define D7_PIN_MASK (const uint16_t)STM_LL_GPIO_PIN(D7_PIN_NAME)<<16
|
|
// Use bit set reset register
|
|
#define D7_BSR(B) D7_PORT->BSRR = D7_PIN_MASK>>(B)
|
|
|
|
// Write 8 bits to TFT for any Nucleo
|
|
#define tft_Write_8(C) D7_BSR(((C)>>3)&0x10); D6_BSR(((C)>>2)&0x10); \
|
|
D5_BSR(((C)>>1)&0x10); D4_BSR(((C)>>0)&0x10); \
|
|
WR_L; \
|
|
D3_BSR(((C)<<1)&0x10); D2_BSR(((C)<<2)&0x10); \
|
|
D1_BSR(((C)<<3)&0x10); D0_BSR(((C)<<4)&0x10); \
|
|
WR_H
|
|
|
|
// Write 16 bits to TFT
|
|
#define tft_Write_16(C) tft_Write_8((C)>>8); tft_Write_8(C)
|
|
|
|
// 16 bit write with swapped bytes
|
|
#define tft_Write_16S(C) tft_Write_8(C); tft_Write_8((C)>>8)
|
|
|
|
#endif // End of parallel/Nucleo 64/144 selections
|
|
|
|
// Write 32 bits to TFT
|
|
#define tft_Write_32(C) tft_Write_16((C)>>16); tft_Write_16(C)
|
|
|
|
// Write two concatenated 16 bit values to TFT
|
|
#define tft_Write_32C(C,D) tft_Write_16(C); tft_Write_16(D)
|
|
|
|
// Write 16 bit value twice to TFT
|
|
#define tft_Write_32D(C) tft_Write_16(C); tft_Write_16(C)
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////
|
|
// Macros to write commands/pixel colour data to a SPI ILI9488 TFT
|
|
////////////////////////////////////////////////////////////////////////////////////////
|
|
#elif defined (ILI9488_DRIVER) // 16 bit colour converted to 3 bytes for 18 bit RGB
|
|
|
|
// Write 8 bits to TFT
|
|
#define tft_Write_8(C) \
|
|
{ spiBuffer[0] = C; \
|
|
HAL_SPI_Transmit(&spiHal, spiBuffer, 1, 10); }
|
|
|
|
// Convert 16 bit colour to 18 bit and write in 3 bytes
|
|
#define tft_Write_16(C) \
|
|
{ spiBuffer[0] = ((C) & 0xF800)>>8; spiBuffer[1] = ((C) & 0x07E0)>>3; spiBuffer[2] = ((C) & 0x001F)<<3; \
|
|
HAL_SPI_Transmit(&spiHal, spiBuffer, 3, 10); }
|
|
|
|
// Convert swapped byte 16 bit colour to 18 bit and write in 3 bytes
|
|
#define tft_Write_16S(C) \
|
|
{ spiBuffer[0] = (C) & 0xF8; spiBuffer[1] = ((C) & 0xE000)>>11 | ((C) & 0x07)<<5; spiBuffer[2] = ((C) & 0x1F00)>>5; \
|
|
HAL_SPI_Transmit(&spiHal, spiBuffer, 3, 10); }
|
|
|
|
// Write 32 bits to TFT
|
|
#define tft_Write_32(C) \
|
|
{ spiBuffer[0] = (C)>>24; spiBuffer[1] = (C)>>16; spiBuffer[2] = (C)>>8; spiBuffer[3] = C; \
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HAL_SPI_Transmit(&spiHal, spiBuffer, 4, 10); }
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// Write two address coordinates
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#define tft_Write_32C(C,D) \
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{ spiBuffer[0] = (C)>>8; spiBuffer[1] = C; spiBuffer[2] = (D)>>8; spiBuffer[3] = D; \
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HAL_SPI_Transmit(&spiHal, spiBuffer, 4, 10); }
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// Write same value twice
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#define tft_Write_32D(C) \
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{ spiBuffer[0] = spiBuffer[2] = (C)>>8; spiBuffer[1] = spiBuffer[3] = C; \
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HAL_SPI_Transmit(&spiHal, spiBuffer, 4, 10); }
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////////////////////////////////////////////////////////////////////////////////////////
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// Macros to write commands/pixel colour data to a SPI Raspberry Pi TFT
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////////////////////////////////////////////////////////////////////////////////////////
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#elif defined (RPI_DISPLAY_TYPE)
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#define tft_Write_8(C) \
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{ spiBuffer[0] = 0; spiBuffer[1] = C; \
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HAL_SPI_Transmit(&spiHal, spiBuffer, 2, 10); }
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#define tft_Write_16(C) \
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{ spiBuffer[0] = (C)>>8; spiBuffer[1] = C; \
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HAL_SPI_Transmit(&spiHal, spiBuffer, 2, 10); }
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#define tft_Write_16S(C) \
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{ spiBuffer[0] = C; spiBuffer[1] = (C)>>8; \
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HAL_SPI_Transmit(&spiHal, spiBuffer, 2, 10); }
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#define tft_Write_32(C) \
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{ spiBuffer[1] = ((C)>>24); spiBuffer[3] = ((C)>>16); spiBuffer[5] = ((C)>>8); spiBuffer[7] = C; \
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HAL_SPI_Transmit(&spiHal, spiBuffer, 8, 10); }
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#define tft_Write_32C(C,D) \
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{ spiBuffer[1] = ((C)>>8); spiBuffer[3] = (C); spiBuffer[5] = ((D)>>8); spiBuffer[7] = D; \
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HAL_SPI_Transmit(&spiHal, spiBuffer, 8, 10); }
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#define tft_Write_32D(C) \
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{ spiBuffer[1] = ((C)>>8); spiBuffer[3] = (C); spiBuffer[5] = ((C)>>8); spiBuffer[7] = C; \
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HAL_SPI_Transmit(&spiHal, spiBuffer, 8, 10); }
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////////////////////////////////////////////////////////////////////////////////////////
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// Macros for all other SPI displays
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////////////////////////////////////////////////////////////////////////////////////////
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#else
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#define tft_Write_8(C) \
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{ spiBuffer[0] = C; \
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HAL_SPI_Transmit(&spiHal, spiBuffer, 1, 10); }
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#define tft_Write_16(C) \
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{ spiBuffer[0] = (C)>>8; spiBuffer[1] = C; \
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HAL_SPI_Transmit(&spiHal, spiBuffer, 2, 10); }
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#define tft_Write_16S(C) \
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{ spiBuffer[0] = C; spiBuffer[1] = (C)>>8; \
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HAL_SPI_Transmit(&spiHal, spiBuffer, 2, 10); }
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#define tft_Write_32(C) \
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{ spiBuffer[0] = (C)>>24; spiBuffer[1] = (C)>>16; spiBuffer[2] = (C)>>8; spiBuffer[3] = C; \
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HAL_SPI_Transmit(&spiHal, spiBuffer, 4, 10); }
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|
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#define tft_Write_32C(C,D) \
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{ spiBuffer[0] = (C)>>8; spiBuffer[1] = C; spiBuffer[2] = (D)>>8; spiBuffer[3] = D; \
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HAL_SPI_Transmit(&spiHal, spiBuffer, 4, 10); }
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|
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#define tft_Write_32D(C) \
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{ spiBuffer[0] = spiBuffer[2] = (C)>>8; spiBuffer[1] = spiBuffer[3] = C; \
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HAL_SPI_Transmit(&spiHal, spiBuffer, 4, 10); }
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|
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#endif
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////////////////////////////////////////////////////////////////////////////////////////
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|
// Macros to read from display using SPI or software SPI
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|
////////////////////////////////////////////////////////////////////////////////////////
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|
#if defined (TFT_SDA_READ)
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|
// Macros to support a bit banged function call for STM32 and bi-directional SDA pin
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|
#define TFT_eSPI_ENABLE_8_BIT_READ // Enable tft_Read_8();
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#define SCLK_L digitalWrite(TFT_SCLK, LOW)
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#define SCLK_H digitalWrite(TFT_SCLK, HIGH)
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#elif !defined (TFT_PARALLEL_8_BIT)
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// Use a SPI read transfer
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|
#define tft_Read_8() spi.transfer(0)
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#endif
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#endif // Header end
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