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Update 16 bit parallel PIO code 

Reduced PIO instruction count
This commit is contained in:
Bodmer 2022-04-23 19:30:47 +01:00
parent 8b272a2cef
commit f9b6633647
2 changed files with 18 additions and 29 deletions
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14
Processors/pio_16bit_parallel.pio
View File

@ -33,6 +33,8 @@ next:
jmp y--, next side 1 jmp y--, next side 1
.wrap_target .wrap_target
// Transmit an 8 bit value (LS 8 bits of 32 bits).
public start_8:
// Transmit a 16 bit value (LS 16 bits of 32 bits). // Transmit a 16 bit value (LS 16 bits of 32 bits).
public start_tx: public start_tx:
// Fetch the next 32 bit value from the TX FIFO and set TFT_WR high. // Fetch the next 32 bit value from the TX FIFO and set TFT_WR high.
@ -43,16 +45,6 @@ public start_tx:
// Set WR high and jump back to start. // Set WR high and jump back to start.
jmp start_tx side 1 jmp start_tx side 1
// Transmit an 8 bit value (LS 8 bits of 32 bits).
public start_8:
// Fetch the next 32 bit value from the TX FIFO and set TFT_WR high.
pull side 1
// Write the first byte (LSB) and sets WR low. This also
// shifts the unused top 16 bits through.
out pins, 32 side 0 [1]
// Jump to start
jmp start_tx side 1
// Transmit a set window command sequence. // Transmit a set window command sequence.
public set_addr_window: public set_addr_window:
// Loop count in x (to send caset, paset and ramwr commands). // Loop count in x (to send caset, paset and ramwr commands).
@ -75,7 +67,7 @@ send_xy:
out pins, 8 side 0 [1] out pins, 8 side 0 [1]
// Loop until 4 bytes sent, TFT_WR high. // Loop until 4 bytes sent, TFT_WR high.
jmp !osre, send_xy side 1 [1] jmp !osre, send_xy side 1 [1]
end_set_addr: end_set_addr: // Jump here since delay needed before DC change
// Loop back for next command and write last command. // Loop back for next command and write last command.
jmp x--, pull_cmd side 1 jmp x--, pull_cmd side 1
// Set DC high. // Set DC high.

33
Processors/pio_16bit_parallel.pio.h
View File

@ -13,12 +13,12 @@
// ------ // // ------ //
#define tft_io_wrap_target 7 #define tft_io_wrap_target 7
#define tft_io_wrap 23 #define tft_io_wrap 20
#define tft_io_offset_block_fill 0u #define tft_io_offset_block_fill 0u
#define tft_io_offset_start_8 7u
#define tft_io_offset_start_tx 7u #define tft_io_offset_start_tx 7u
#define tft_io_offset_start_8 10u #define tft_io_offset_set_addr_window 10u
#define tft_io_offset_set_addr_window 13u
static const uint16_t tft_io_program_instructions[] = { static const uint16_t tft_io_program_instructions[] = {
0x98a0, // 0: pull block side 1 0x98a0, // 0: pull block side 1
@ -32,27 +32,24 @@ static const uint16_t tft_io_program_instructions[] = {
0x98a0, // 7: pull block side 1 0x98a0, // 7: pull block side 1
0x7100, // 8: out pins, 32 side 0 [1] 0x7100, // 8: out pins, 32 side 0 [1]
0x1807, // 9: jmp 7 side 1 0x1807, // 9: jmp 7 side 1
0x98a0, // 10: pull block side 1 0xf822, // 10: set x, 2 side 1
0x7100, // 11: out pins, 32 side 0 [1] 0xe000, // 11: set pins, 0
0x1807, // 12: jmp 7 side 1 0x80a0, // 12: pull block
0xf822, // 13: set x, 2 side 1 0x7000, // 13: out pins, 32 side 0
0xe000, // 14: set pins, 0 0x0033, // 14: jmp !x, 19
0x80a0, // 15: pull block 0x98a0, // 15: pull block side 1
0x7000, // 16: out pins, 32 side 0 0xe001, // 16: set pins, 1
0x0036, // 17: jmp !x, 22 0x7108, // 17: out pins, 8 side 0 [1]
0x98a0, // 18: pull block side 1 0x19f1, // 18: jmp !osre, 17 side 1 [1]
0xe001, // 19: set pins, 1 0x184b, // 19: jmp x--, 11 side 1
0x7108, // 20: out pins, 8 side 0 [1] 0xe001, // 20: set pins, 1
0x19f4, // 21: jmp !osre, 20 side 1 [1]
0x184e, // 22: jmp x--, 14 side 1
0xe001, // 23: set pins, 1
// .wrap // .wrap
}; };
#if !PICO_NO_HARDWARE #if !PICO_NO_HARDWARE
static const struct pio_program tft_io_program = { static const struct pio_program tft_io_program = {
.instructions = tft_io_program_instructions, .instructions = tft_io_program_instructions,
.length = 24, .length = 21,
.origin = -1, .origin = -1,
}; };