Updates for ESP32-S3 Compatability

Added Feather.h mappings; and
Changed RMT clock logic in RFControl to check for presence of RMT_SYS_CON_REG instead of simply looking for CONFIG_IDF_TARGET_ESP32C3;

** NOTE:  Can ignore warnings about RMT_CH4...CH7+RX_LIM_REG redefine errors.  This has been reported to Espressif IDF Github, been acknowledged as a bug, and will be fixed in a future release of the IDF.  Since HomeSpan does NOT use the RMT peripheral for RECEIVING, these warning messages have no effect.

src/FeatherPins.h

@@ -31,15 +31,39 @@
 #pragma once
 
 #if defined(ARDUINO_FEATHER_ESP32)
-  enum {F13=13,F12=12,F27=27,F33=33,F15=15,F32=32,F14=14,F22=22,F23=23,F26=26,F25=25,F34=34,F39=39,F36=36,F4=4,F5=5,F18=18,F19=19,F16=16,F17=17,F21=21};
+  enum {
+    F13=13,F12=12,F27=27,F15=15,F32=32,F14=14,F16=16,F17=17,F21=21,   // Digital Only (9 pins)
+    F26=26,F25=25,F34=34,F39=39,F36=36,F4=4,                          // A0-A5
+    F22=22,F23=23,                                                    // I2C SCL/SDA
+    F5=5,F18=18,F19=19,F33=33                                         // SPI SCK/SDO/SDI/CS
+  };
   #define DEVICE_SUFFIX ""
 
 #elif defined(ARDUINO_ESP32S2_DEV)
-  enum {F13=1,F12=3,F27=7,F33=34,F15=10,F32=42,F14=11,F22=9,F23=8,F26=17,F25=14,F34=13,F39=12,F36=18,F4=19,F5=36,F18=35,F19=37,F16=20,F17=21,F21=16};
+  enum {
+    F13=1,F12=3,F27=7,F15=10,F32=42,F14=11,F16=20,F17=21,F21=16,      // Digital Only (9 pins)
+    F26=17,F25=14,F34=13,F39=12,F36=18,F4=19,                         // A0-A5
+    F22=9,F23=8,                                                      // I2C SCL/SDA
+    F5=36,F18=35,F19=37,F33=34                                        // SPI SCK/SDO/SDI/CS
+  };
   #define DEVICE_SUFFIX "-S2"
 
 #elif defined(ARDUINO_ESP32C3_DEV)
-  enum {F27=2,F33=7,F32=3,F14=10,F22=9,F23=8,F26=0,F25=1,F4=18,F5=4,F18=6,F19=5,F16=20,F17=21,F21=19};
+  enum {
+    F27=2,F32=3,F14=10,F16=20,F17=21,F21=19,                          // Digital Only (6 pins)
+    F26=0,F25=1,F4=18,                                                // A0/A1/A5
+    F22=9,F23=8,                                                      // I2C SCL/SDA
+    F5=4,F18=6,F19=5,F33=7                                            // SPI SCK/SDO/SDI/CS
+    };
   #define DEVICE_SUFFIX "-C3"
 
+#elif defined(ARDUINO_ESP32S3_DEV)
+  enum {
+    F13=5,F12=6,F27=7,F15=16,F32=17,F14=18,F16=37,F17=36,F21=35,      // Digital Only (9 pins)
+    F26=1,F25=2,F34=20,F39=19,F36=15,F4=4,                            // A0-A5
+    F22=9,F23=8,                                                      // I2C SCL/SDA
+    F5=12,F18=11,F19=13,F33=10                                        // SPI SCK/SDO/SDI/CS
+  };
+  #define DEVICE_SUFFIX "-S3"
+  
 #endif

src/extras/RFControl.cpp

@@ -64,8 +64,8 @@ RFControl::RFControl(uint8_t pin, boolean refClock, boolean installDriver){
   this->refClock=refClock;
   
   if(refClock)
-#ifdef CONFIG_IDF_TARGET_ESP32C3
+#ifdef RMT_SYS_CONF_REG
-  REG_SET_FIELD(RMT_SYS_CONF_REG,RMT_SCLK_DIV_NUM,79);        // ESP32-C3 does not have a 1 MHz REF Tick Clock, but allows the 80 MHz APB clock to be scaled by an additional RMT-specific divider
+  REG_SET_FIELD(RMT_SYS_CONF_REG,RMT_SCLK_DIV_NUM,79);        // ESP32-C3 and ESP32-S3 do not have a 1 MHz REF Tick Clock, but allows the 80 MHz APB clock to be scaled by an additional RMT-specific divider
 #else  
   rmt_set_source_clk(config->channel,RMT_BASECLK_REF);        // use 1 MHz REF Tick Clock for ESP32 and ESP32-S2
 #endif